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ECET 340 Operation of the HCS12 Timer Unit | Complete Solution
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DeVry University –– ECET 340
Name(s):

Team or Group #(if applicable):    Professor:
Experiment or Assignment #: 3    Lab Meeting Day & Time:

Title of Report:
Operation of the HCS12 Timer Unit

Summary (two sentences):


________________________________________________________________________
Checklist (items included):
1. Introduction & Background        4. Results: Data, Tables, & Diagrams    
2. Procedure         5. Analysis of Results    
3. Troubleshooting & Testing        6. Conclusions     
Key Results:


________________________________________________________________________
Key Conclusions (technical):


________________________________________________________________________
Key Conclusions (critical thinking):


________________________________________________________________________

Date Due:
    Date Submitted:
Student(s) Signature:
    Professor’s Signature:
I.         OBJECTIVES

1.    To understand the basic functions performed by an embedded timer

2.    To learn how to program the various modes of timer operation in C language

3.    To learn how to use the timer to measure time intervals and to produce digital waveforms of specified frequency and duty cycle.     


II.         PARTS LIST

Equipment:
IBM PC – Pentium or compatible
    Codewarrior v. 5.9.0  
        Oscilloscope
    Waveform Generator
    
Parts:
    1- Wytec EVBPlus Microcontroller Demonstration Board Kit, including:
         MC9S12DG256 demonstration board
         USB cable and adapter
         Universal power supply and cable
         MC9S12DG256 Development Boards CD


III.         INTRODUCTION

The embedded timer is an example of an internal peripheral – a dedicated circuit function fully integrated into the HCS12.  The timer unit can function as an input device or an output device, or as both simultaneously.  As an input device, it can be used to time or count external events; as an output device it can generate waveforms or delays to control external devices such as speakers or actuators.  Since the timer is an internal device, the only hardware interface needed is the connection of timer input and/or output pins to their various applications.   
The five major functions performed by the HC12 timer are: input capture (IC), output compare (OC), real-time interrupt (RTI), pulse accumulation (PA), and pulse-width modulation (PWM).  IC and PA measure timer inputs; OC and PWM generate timer outputs.  RTI generates processor interrupts periodically.  This lab explores two of the functions: IC and PWM.      
A.  Timer Block Diagram and Programming Registers  
Figure 1 is a block diagram of the HCS12 Timer unit.  It uses two time bases, primary and secondary, for all timing operations.  The primary time base is the free-running 16-bit up counter (main timer).  Its counting speed is adjusted for specific applications by programming 3 pre-scale bits in the TSCR2 register (see Figures 2 and 3).  These bits are used to divide the incoming e-clock frequency reference by a factor ranging from 1 to 128.  The HCS12 e-clock speed is 24 MHz on the EVBPlus board, so main timer frequencies can range from 24 MHz down to 187.5 kHz.  

 
The current time (16-bit count state of the main timer) can be read out at any time from the TCNT register.  Counting in the timer is enabled (disabled) by setting (resetting) the TEN bit in the TSCR1 register.  When the counter reaches its terminal count state of 0xFFFF, it automatically rolls over to 0x0000 and continues counting.
Symbolic Name    Register Name    Offset Address
TSCR1    Timer System Control 1    $0046
TSCR2    Timer System Control 2    $004D
TCNT     Timer Counter     $0044 (16-bits)

Figure 2 – Timer Control Registers
d7    d6    d5    d4    d3    d2    d1    d0

TEN    TSWAI    TSFRZ    TFFCA    0    0    0    0

TEN – Timer enable: ‘1’ enables the counter to operate; ‘0’ disables the counter.
TFFCA – Timer fast flag clear all:  (automatically clear flags when associated register is read)
‘1’ means that the input capture channel flag is cleared automatically each time the value is input from the appropriate register.
‘0’ means that the flag must be cleared under program control.  
d7    d6    d5    d4    d3    d2    d1    d0

TOI    0    0    0    TCRE    PR2    PR1    PR0

TOI – Timer Overflow Interrupt: ‘1’ enables processor interrupt whenever counter overflows; ‘0’ inhibits the interrupt.
PR2 PR1 PR0 – Pre-scale factor [3]:  Divide e-clock frequency by power of 2 coded in binary
PR2  PR1  PR0    000    001    010    011    100    101    110    111
e-Clock Divisor    1    2    4    8    16    32    64    128
Timer frequency (MHz)    24     12     6     3    1.5     0.75    0.375    0.1875

d15    d14    d13    d12    d11    d10    d9    d8    d7    d6    d5    d4    d3    d2    d1    d0


    
                                        
    

Figure 3– Timer Programming Registers

 

 
 


B.   Input Capture Programming Registers
Input capture can be used to measure the frequency, period, pulse-width, duty cycle and phase difference of incoming waveforms.  Figure 4 reviews the meanings of these parameters.  Port T is used for this and all other timer functions except PWM.  Each pin of Port T is associated with one of the 8 independent timer channels; for example, pin PT0 inputs waveforms to channel 0, etc.  A channel is enabled for input capture in the TIOS register.
T = period
PW = pulsewidth  (active-HI)
f = 1/T     frequency
% duty = (PW/ T) x100%  =  duty cycle

 

Figure 4 - Waveform Parameters
Input capture latches a copy of the main timer count into the 16-bit timer input capture register (TC0 for channel 0, etc., see Figures 5 and 6) each time an edge event is detected on the input waveform.  A flag-bit (CF0 for ch. 0, etc.) in the TFLG1 register is set to ‘1’ after each edge to let the program know it is time to read out TC0.  Unread data is automatically overwritten by the next incoming edge.  Active edges are selected as either rising edge (RE) or falling edge (FE) by the EDG bits in the TCTL3 and 4 registers.
Symbolic Name    Register Name    Offset Address
TIOS    Timer I/O Select    $0040
TCTL3, TCTL4    Timer Control 3 and 4    $004A, $004B
TFLG1    Timer Interrupt Flag 1    $004E
TFLG2    Timer Interrupt Flag 2    $004F
TIE     Timer Interrupt Enable     $004C
TC0 to TC7    Timer Input Capture / Output Compare    $0050-$005E

 

 


Figure 5 – Input Capture Registers
Single edge events can be captured one after another in the manner just described and subtracted from one another to find the time difference (in main timer counts) between them.  Both period T and pulse width PW can be found this way.  Also, the phase difference between two waveforms arriving in separate timer channels can be calculated by subtracting the main timer counts latched into their respective TC registers.       
Each of the 8 timer input channels can be enabled for edge-activated processor interrupt by setting the associated bit in the timer interrupt enable (TIE) register.  These interrupts, as well as the timer overflow interrupt (enabled in TSCR2), have vector table entries and are maskable in software by setting the I-bit in the CPU’s flag (CCR) register.


d7    d6    d5    d4    d3    d2    d1    d0

IOS7    IOS6    IOS5    IOS4    IOS3    IOS2    IOS1    IOS0
IOS[7:0] –  Timer Input Capture / Output Compare Select
‘1’ enables corresponding channel for output compare
‘0’ enables corresponding channel for input capture

d15    d14    d13    d12    d11    d10    d9    d8    d7    d6    d5    d4    d3    d2    d1    d0

 

                                                

TCN [15:0] –  Timer Input Capture / Output Compare (8 of them, one for each channel)

  d7    d6    d5    d4    d3    d2    d1    d0

C7F    C6F    C5F    C4F    C3F    C2F    C1F    C0F

TOF    0    0    0    0    0    0    0
C7F-C0F – Timer Interrupt Flag Control:
‘1’ means an edge has been captured. A flag is cleared by writing a ‘1’ to it (or by FFCA)
TOF  - ‘1’ means the main timer overflowed (rolled over to 0x0000 from terminal count)
 
d7    d6    d5    d4    d3    d2    d1    d0

EDG7B    EDG7A    EDG6B    EDG6A    EDG5B    EDG5A    EDG4B    EDG4A

EDG3B    EDG3A    EDG2B    EDG2A    EDG1B    EDG1A    EDG0B    EDG0A
EDGx[B:A] –  Timer Control (edge selection):
EDGB    EDGA    Edge Configuration
0    0    Disable edge capture
0    1    Capture on rising edges only
1    0    Capture on falling edges only
1    1    Capture on any edge (rising or falling)

d7    d6    d5    d4    d3    d2    d1    d0

C7I    C6I    C5I    C4I    C3I    C2I    C1I    C0I
C7F-C0F – Timer Interrupt Enable:
‘1’ enables corresponding channel for edge-triggered interrupt
‘0’ disables interrupt on this channel
Figure 6 - Input Capture Programming Registers
C.    Pulse Width Modulator Block Diagram and Programming Registers
The pulse width modulator (PWM) generates waveforms with programmable frequency and duty cycle on the pins of Port P.  It has 8 independent output channels, each with its own period register, duty cycle register and output pin (see Figure 8).  Once a channel is enabled, it continues to output until it is disabled.  Multiple channels can output at once.  Key PWM programming registers are shown in Figures 9 and 10.

 

 

 

 

 

 

 

Figure 8 -Pulse Width Modulator Unit
Symbolic Name    Register Name    Offset Address
PWMCLK    PWM Clock Select    $00A2
PWMPRCLK    PWM Pre-scale Clock Select    $00A3
PWMPOL    PWM Polarity     $00A1
PWMCTL    PWM Control    $00A5
PWMPER0 to 7    PWM Period    $00B4-$00BB
PWMDTY0 to 7    PWM Duty Cycle    $00BD-$00C3
PWME    PWM Enable    $00A0
Figure 9 - Pulse Width Modulator Unit Programming Registers

d7    d6    d5    d4    d3    d2    d1    d0

PCLK7    PCLK6    PCLK5    PCLK4    PCLK3    PCLK2    PCLK1    PCLK0
PCLK7, PCLK6, PCLK3, PCLK2 – ‘1’ selects clock SB; ‘0’ selects clock B for that channel
PCLK5, PCLK4, PCLK1, PCLK0 – ‘1’ selects clock SA; ‘0’ selects clock A for that channel

d7    d6    d5    d4    d3    d2    d1    d0

0    PCKB2    PCKB1    PCKB0    0    PCKA2    PCKA1    PCKA0
PCKB[2:0] – Clock pre-scale bits for clock B
PCKA[2:0] – Clock pre-scale bits for clock A
PCK2    PCK1    PCK0    e-Clock Divisor     [frequency for 24 MHz e-clock]
0    0    0    1          [24 MHz]
0    0    1    2          [12 MHz]
0    1    0               4           [6.0 MHz]  etc…
1    1    1    128         [187.5 kHz]

d7    d6    d5    d4    d3    d2    d1    d0

PPOL7    PPOL6    PPOL5    PPOL4    PPOL3    PPOL2    PPOL1    PPOL0
PPOL – Polarity:  ‘1’ means output is HIGH at beginning of cycle and goes LOW at the end
                 ‘0’ means output is LOW at beginning of cycle and goes HIGH at the end

d7    d6    d5    d4    d3    d2    d1    d0

CON67    CON45    CON23    CON01    PSWAI    PFRZ    0    0
CON  –  Concatenate the two 8-bit channels shown into a single 16-bit circuit that outputs on the higher channel’s pin.  ‘1’ means concatenate; ‘0’ disables concatenation

d7    d6    d5    d4    d3    d2    d1    d0

PWME7    PWME6    PWME5    PWME4    PWME3    PWME2    PWME1    PWME0
PWME –  ‘1’ enables associated channel to output pulses; ‘0’ disables it

d7    d6    d5    d4    d3    d2    d1    d0

d7    d6    d5    d4    d3    d2    d1    d0          

 

The PWM function is designed to allow for a very large range of clock frequencies to create the signals. There are registers for both a pre-scalar (up to 1/128) and a scalar (up to 1/512) for the clock. This gives possible MOD numbers from 1 up to 65,536.
Four different clock sources can be used by the PWM counters.  They are designated as clock A, clock B, clock SA (Scaled A), and clock SB (Scaled B). Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8, . . . ,1/128 slower than the e-clock. The SA and SB clocks use clock A and B respectively, and allow further division by up to 512 in increments of divide by 2.   
IV.         PROCEDURE


A.  Pulse Width Modulator Function
1.    Enter the code pwm_test.c shown below.  Connect the oscilloscope to Port P, bit 0 (PP0).  
2.    Run the program and verify that the output is a 100 kHz waveform with 50% duty cycle.

// pwm_test.c

// PWM0 generates 100 kHz, 50% duty cycle waveform on Port P pin 0
// Wytec HC12 Dev Board (24MHz e-clk) using Codewarrior - tested 5-9-2009kj  
// Configures PWM to generate continuous 100 kHz waveform, 50% duty cycle
// Output: Port P - pin 0 (PP0) connects to oscilloscope input

/* Open jumper J24 to disable 7-segment LED connection to pin PP0 */

#include <hidef.h>      /* common defines and macros */
#include <mc9s12dg256.h>     /* derivative information */
#pragma LINK_INFO DERIVATIVE "mc9s12dg256b"


void main(void) {
//  EnableInterrupts;
       PWMCLK = 0x00;   // Ch. 0 source: clock A, pre-scale = 1
     PWMPOL = 0x01;   // initial HIGH output (left-align) on ch. 0        
     PWMCTL = 0x00;  // 8-bit PWM counter, period and duty cycle registers
     PWMPER0 = 240;      // period value = 10 us   (24MHz/100kHz)
     PWMDTY0 = 120;    // signal high = 5 us    (0.50 x 240)
     PWME |= 0x01;      // turn-on PWM ch. 0

    for(;;) {} /* wait forever */
}

/********* end of code ********/

 

Design Project
Write and test a C program that outputs a waveform that switches from 10.0 kHz with a 50% duty cycle to 25.0 kHz with a 5% duty cycle every 5 seconds.  Your code design must be modular – initializations and program operations are to be performed by calling functions.  Comment key lines of code and answer the questions below.  Include a copy of an oscilloscope read out of the waveform (online) or have your instructor sign-off your project (onsite).

Instructor Sign-off______________________ .

 
V.         TROUBLESHOOTING

Describe any problems encountered and how those problems were solved.


VI.         QUESTIONS

1.    Which of your timer period measurements did you find to be closer to the actual period of your input waveform, those at higher frequencies or those at lower frequencies?  Why?  [Hint: Examine the edges of the input waveform on the oscilloscope as you vary generator frequency]

 

2.    Write down the statements that you need to send to Input Capture registers in order to enable Port T pin 5 for interrupt service.  Assume a falling-edge trigger is to be used.


3.    Write down the modifications needed to statements in the file period.c for measuring duty cycle instead of period.  

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ECET 340 Operation of the HCS12 Timer Unit | Complete Solution
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  • Submitted On 27 Sep, 2015 03:08:36
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PWMPER0 = 240; // period value = 10...
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